Palo Alto, United States
Physical Design Engineer
Voltai · Palo Alto · United States
Posted: 10/19/2026 · Last checked: 10/21/2026
Job description
Quoted in full from Voltai's job posting. Gavroche does not edit it.
About Voltai
Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.
About the Team
Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.
About this Role
You'll take designs from netlist to GDSII. You'll own floorplanning through closure on real silicon programs with leading semiconductor companies while helping Voltai's AI learn how expert physical designers make decisions.
What You’ll Do
Own block-level and full-chip physical implementation: floorplanning, placement, clock tree synthesis, and routing.
Drive timing, power, and congestion closure with synthesis and STA teams.
Close physical verification (DRC/LVS) and power integrity (IR drop, EM) for signoff.
Build and improve place-and-route flows and automation.
Evaluate AI-generated floorplans and implementation decisions, and help define what good looks like.
Work directly with customer teams on implementation challenges.
What We’re Looking For
5+ years of physical design experience with multiple production tapeouts.
Deep experience with Innovus or Fusion Compiler/ICC2.
Strong understanding of timing closure, clock tree synthesis, and power distribution networks.
Experience at advanced nodes (7nm and below).
Strong Tcl and Python scripting.
Bonus Points
Full-chip integration or hierarchical design experience.
Experience with high-speed or low-power designs.
Interest in AI or machine learning applied to physical design.
Similar roles in Palo Alto
- Design for Test - DFT - Engineer · Voltai, Palo Alto
- RTL Design Engineer · Voltai, Palo Alto
- Principal DFT Engineer - Silicon Engineering · SpaceX, Palo Alto
- ASIC/SOC DFT Engineer - Silicon Engineering · SpaceX, Palo Alto
- Sr. ASIC DFT Engineer - Silicon · SpaceX, Palo Alto
- Sr. Physical Design Engineer · Lumilens, San Jose
61 open roles like this one; at most three per employer shown.
What chip design / verification engineer adverts in the United States state
Middle half: 150,375 – 215,625 USD a year; median 172,500 USD.
From 42 adverts by 17 employers that state a salary, annualised.
New openings in Palo Alto, by week
- 7/27/2026 13
- 8/3/2026 33
- 8/10/2026 22
- 8/17/2026 21
- 8/24/2026 30
- 8/31/2026 27
- 9/7/2026 23
- 9/14/2026 29
- 9/21/2026 42
- 9/28/2026 51
- 10/5/2026 42
- 10/12/2026 49
- 10/19/2026 43
425 openings over 12 weeks, by the week they were published.
Other roles at Voltai
- CAD & Flow Methodology Engineer · Palo Alto
- Design for Test - DFT - Engineer · Palo Alto
- Physical Verification & Signoff Engineer · Palo Alto
- Post-Silicon Validation Engineer · Palo Alto
- Synthesis & Static Timing Analysis - STA - Engineer · Palo Alto
- Chip Architect · Palo Alto
29 open.