Palo Alto, United States
Design for Test - DFT - Engineer
Voltai · Palo Alto · United States
Posted: 10/19/2026 · Last checked: 10/21/2026
Job description
Quoted in full from Voltai's job posting. Gavroche does not edit it.
About Voltai
Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.
About the Team
Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.
About this Role
You'll make sure the chips we work on can be tested in manufacturing and in the field. You'll own DFT architecture and implementation on real silicon programs with leading semiconductor companies while helping Voltai's AI learn DFT methodology.
What You’ll Do
Define DFT architecture for SoCs and IP, including scan, compression, MBIST, LBIST, and boundary scan.
Insert and verify DFT logic, and generate ATPG patterns that meet coverage targets.
Work with RTL, synthesis, and physical design teams to close DFT timing and area impact.
Support silicon bring-up, pattern debug, and yield analysis with test and product engineering.
Build automation for DFT flows and coverage reporting.
Help define how AI can accelerate DFT insertion and pattern generation.
What We’re Looking For
5+ years of DFT experience on production tapeouts.
Hands-on experience with Tessent, TestMAX, or Modus.
Strong knowledge of scan, compression, ATPG, MBIST, and IEEE 1149.1/1687.
Experience with DFT verification and gate-level simulation.
Tcl and Python scripting.
Bonus Points
Post-silicon test bring-up and ATE experience.
Experience with 2.5D/3D or chiplet test strategies.
Interest in AI-assisted design tools.
Similar roles in Palo Alto
- RTL Design Engineer · Voltai, Palo Alto
- Physical Design Engineer · Voltai, Palo Alto
- Principal DFT Engineer - Silicon Engineering · SpaceX, Palo Alto
- Sr. ASIC DFT Engineer - Silicon · SpaceX, Palo Alto
- ASIC/SOC DFT Engineer - Silicon Engineering · SpaceX, Palo Alto
- IC/RTL Design Engineer · Lumilens, San Jose
61 open roles like this one; at most three per employer shown.
What chip design / verification engineer adverts in the United States state
Middle half: 150,375 – 215,625 USD a year; median 172,500 USD.
From 42 adverts by 17 employers that state a salary, annualised.
New openings in Palo Alto, by week
- 7/27/2026 13
- 8/3/2026 33
- 8/10/2026 22
- 8/17/2026 21
- 8/24/2026 30
- 8/31/2026 27
- 9/7/2026 23
- 9/14/2026 29
- 9/21/2026 42
- 9/28/2026 51
- 10/5/2026 42
- 10/12/2026 49
- 10/19/2026 44
426 openings over 12 weeks, by the week they were published.
Other roles at Voltai
- Physical Verification & Signoff Engineer · Palo Alto
- Post-Silicon Validation Engineer · Palo Alto
- CAD & Flow Methodology Engineer · Palo Alto
- RTL Design Engineer · Palo Alto
- Chip Architect · Palo Alto
- Synthesis & Static Timing Analysis - STA - Engineer · Palo Alto
29 open.