RTL Design Engineer

About Etched

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep chain-of-thought reasoning.

RTL Design Engineer

As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips operate correctly and efficiently. You will develop and implement design verification strategies for both our existing and upcoming ASIC designs.

In this role, you will work closely with state-of-the-art architectures for machine learning. You do not need to have experience working with these yet, but you will be willing and able to learn quickly. You will work in a fast-paced environment with a high degree of autonomy, and be responsible for a key part of Etched’s success.

Representative projects:

• Implement a block to efficiently compute floating point math operators
• Provide feedback to the uArch team to make sure blocks meet timing and area constraints

You may be a good fit if you:

• At least 5 years of work experience in RTL development.
• Experience with high-speed digital logic.
• Proficiency in standard RTL design and synthesis tools
• Familiarity with verification work and writing test benches
• Are able to learn quickly about transformers and other aspects of modern artificial intelligence
• Willing to start quickly

Strong candidates may also have experience with:

• Experience with PCIe, Ethernet, or HBM technologies
• Familiarity with transformer models and machine learning.
• Familiarity with numerical representations and functions
• ​Ability to program with Python or another scripting language

We encourage you to apply even if you do not believe you meet every single qualification.

How we’re different:

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

Benefits:

• Full medical, dental, and vision packages, with 100% of premium covered, 90% for dependents
• Housing subsidy of $2,000/month for those living within walking distance of the office
• Daily lunch and dinner in our office
• Relocation support for those moving to Cupertino