Posted by the employer · San Jose, United States
RFIC Design Intern
SkyGig · San Jose · United States
Posted: 6/29/2026 · On the employer's job feed since 10/11/2026
The advert
Quoted in full from SkyGig's job posting. Gavroche does not edit it.
We are seeking a motivated RFIC Design Engineer Intern to support the development, simulation, and validation of RF integrated circuits for next-generation wireless and satellite communications applications. This internship is ideal for a student with strong fundamentals in analog/RF circuit design who wants hands-on experience working with experienced RFIC engineers on real product development and help push new hardware innovations forward.
Responsibilities
As an RFIC Design Engineer Intern, you will:
- Assist with the design and simulation of RF/analog front-end circuit blocks such as LNAs, mixers, oscillators, PLLs, PAs, VGAs, switches, etc.
- Perform circuit RF simulations including S-parameters, noise figure, gain, linearity, stability, power consumption, etc.
- Support layout reviews, parasitic extraction, and post-layout simulations.
- Assist in the analysis of 2.5D and 3D EM circuit models and simulation outcomes.
- Work across a cross-functional collaborative team of bright RF engineers.
- Prepare technical documents and reports, and participate in design reviews and brainstorming sessions.
We are considering full-time/ part-time applicants for Fall 2026.
The ideal candidate will have strong technical competency, curiosity, and the ability to take the lead and ownership of a well-defined project. They should also be excited to adapt, learn quickly, and grow in a fast-paced startup environment.
Requirements
- Currently pursuing a M.S., or Ph.D. in Electrical Engineering with 2+ years of RFIC design experience.
- Strong background in RF state-of-the-art CMOS, SOI, or SiGe technologies
- Proficient in RFIC design and characterization tools such as Cadence Virtuoso, Spectre RF, ADS, or similar.
- Deep understanding of system specifications and capable of translating system requirements into circuit requirements at IC level.
- Experience with RFIC layout and post-layout simulation.
- Experience with Python, MATLAB, or scripting for data analysis and automation.
- Prior research, or tapeout experience in RF/analog IC design.
- Comfortable working and solving problems independently as well as collaboratively within a team.
- Strong written and oral communication skills in English and comfortable explaining technical concepts to the rest of the team.
Benefits
- Paid, full-time, onsite internship at our Bay Area, CA location with competitive salary
- Opportunity to work with a collaborative and ambitious team developing disruptive products.
- Opportunities for growth, leadership, and project ownership in a dynamic startup environment.
Similar roles in San Jose
- Electrical Engineering Intern - Summer 2027 · Muon Space, San Jose
- Environmental Test Engineering Intern - Summer 2027 · Muon Space, San Jose
- Validation Engineering Intern [Winter 2027] · Figure, San Jose
- Services Portfolio Management Intern- Summer 2027 · Veeam Software, San Jose
- AI/ML Intern Summer 2027 · Veeam Software, San Jose
- Firmware Engineering Intern [Winter 2027] · Figure, San Jose
200 open intern (generic) roles found; at most three per employer shown. Source: Direct employer job feeds (ATS) and career sites crawled by gavroche-direct.
How intern (generic) roles in United States are worked
0% fully remote · 1% hybrid · 99% on-site
From 300 adverts whose ATS states a work mode. Source: Direct employer job feeds (ATS) and career sites crawled by gavroche-direct; the employers' own work-mode flags (adverts without one count as on-site).
New roles in San Jose, last 12 weeks
- 7/20/2026 28
- 7/27/2026 48
- 8/3/2026 39
- 8/10/2026 29
- 8/17/2026 54
- 8/24/2026 45
- 8/31/2026 59
- 9/7/2026 51
- 9/14/2026 54
- 9/21/2026 55
- 9/28/2026 59
- 10/5/2026 55
576 vacancies. Source: Direct employer job feeds (ATS) and career sites crawled by gavroche-direct; vacancies by their own publication week.