San Jose, United States
Physical Design Engineer
Etched · San Jose · United States
Posted: 8/11/2025 · Last checked: 10/18/2026
Job description
Quoted in full from Etched's job posting. Gavroche does not edit it.
About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
Etched is looking for exceptional Physical Design engineers to join our team. In this role, you
will own block-level implementation and verification, drive timing closure and PPA optimization, supervise 3rd party design work, and help improve our design flows and iteration speed.
Key Responsibilities
Deeply understand what is involved in physical design
Running PD flows to close blocks, support ASIC infrastructure, automate PD flows,
improve CAD infrastructureCollaborate with RTL Designers and provide Physical Design feedback to improve PPA
Drive dashboards that show the convergence of projects related to PD
Optimize tool flows, working with EDA vendors to incorporate the latest features
Accountable for block level closure
Supervise the outsourcing of physical design to a 3rd party service
You may be a good fit if you have
5-10+ years of previous experience with PD
Tools, flow, and design methodology from RTL synthesis to GDSII sign-off
Experience with back-end design and timing closure on advanced process nodes (5nm
and below)Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler)
automated RTL-to-GDSII flowsExperience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
Experience with UPF-based low power design methodology, power verification,synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS,
routing, IR drop, and EM/antenna analysisDeeply creative and able to think from first principles
Strong candidates may also have experience with
Familiarity with modern ML and LLM model architectures
Ability to program with Python or another scripting language
Familiarity with AI tools for programming/coding
Startup experience or comfort working in fast-paced environments
Benefits
Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Housing subsidy of $2.5k per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch + dinner in our office
Unlimited compute budget subject to ROI justification
How we’re different:
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.
Similar roles in San Jose
- IC/RTL Design Engineer · Lumilens, San Jose
- Sr. Physical Design Engineer · Lumilens, San Jose
- Physical Design Engineer - Flow & Methodologies · Etched, San Jose
- Physical Design Engineer - Full Chip Implementation · Etched, San Jose
- RTL Design Engineer · Etched, San Jose
- Staff HSIO Digital & Mixed Signal Design Engineer · Samsung Semiconductor, San Jose
59 open roles like this one; at most three per employer shown.
What chip design / verification engineer adverts in the United States state
Middle half: 150,375 – 215,625 USD a year; median 172,500 USD.
From 42 adverts by 17 employers that state a salary, annualised.
New openings in San Jose, by week
- 7/20/2026 37
- 7/27/2026 52
- 8/3/2026 43
- 8/10/2026 30
- 8/17/2026 55
- 8/24/2026 48
- 8/31/2026 64
- 9/7/2026 48
- 9/14/2026 52
- 9/21/2026 51
- 9/28/2026 55
- 10/5/2026 87
- 10/12/2026 106
728 openings over 12 weeks, by the week they were published.
Other roles at Etched
- Demand Planner · San Jose
- Senior Manufacturing Software Engineer · San Jose
- Developer Experience Engineer · San Jose
- Infrastructure Software Engineer · San Jose
- Silicon Validation Engineer - Software · San Jose
- Internal Acceleration - Engineer - Special Projects · San Jose
120 open.