Design Verification Engineer

Responsibilities:

• • Develop comprehensive verification plans aligned with design and system requirements.
  • Perform functional verification of custom mixed-signal ASICs at block and chip level.
  • Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and assertions.
  • Create directed and constrained-random test suites to ensure robust functional coverage.
  • Implement, analyze, and drive functional and code coverage, including coverage closure.
  • Conduct failure analysis, regression triage, and debug, resolving functional and timing-related issues.
  • Run and debug gate-level simulations, including timing violations and back-annotation issues.
  • Develop and maintain digital and mixed-signal behavioral models to support verification.
  • Support verification flow and infrastructure development, including regressions and automation.
  • Collaborate cross-functionally with digital/analog design, systems, applications, firmware/software, and manufacturing test teams.
  • Contribute to both pre-silicon verification and post-silicon validation efforts.
  • Proactively improve verification methodologies, processes, and best practices.

Required Knowledge, Skills, and Experience:

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
• • Bachelor’s with 2+ years of relevant experience.
  • Master’s with 0+ years of relevant experience.
  • Significant industry experience in silicon design and/or ASIC verification.
  • Strong proficiency with HDLs: Verilog and/or VHDL.
  • Strong proficiency with HVLs: SystemVerilog with UVM (or OVM/AVM/Vera).
  • Solid understanding of digital design principles and system architecture.
  • Hands-on experience with:
  • • Testbench architecture and stimulus generation
    • Regression execution and debug
    • Coverage analysis and closure
    • Ability to work effectively in a cross-disciplinary, team-oriented environment.

Preferred Knowledge, Skills, and Experience:

• Experience verifying mixed-signal ASICs in complex SoC environments.
• Knowledge of signal processing concepts relevant to mixed-signal designs.
• Experience with SystemVerilog Assertions (SVA).
• Exposure to or hands-on experience with:
• • Formal verification
  • Hardware emulation or acceleration
  • Software-driven verification
  • Demonstrated ability to evaluate, debug, and improve verification flows and methodologies.