Posted by the employer · Bengaluru, India
Silicon Design Architect
Astera Labs · Bengaluru · India
Posted: 22/9/2026 · On the employer's job feed since 11/10/2026
The advert
Quoted in full from Astera Labs's job posting. Gavroche does not edit it.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Silicon Digital Architect - IP / Subsystem
Experience- 20+ years
Job Summary
We are looking for an experienced IP/Subsystem Architect to define the architecture and technical direction of complex semiconductor IPs and subsystems. The candidate will own architecture definition from requirements through implementation, working closely with SoC, RTL, verification, physical design, firmware, and system teams.
Key Responsibilities
- Define architecture for complex IP blocks and SoC subsystems based on product and system requirements.
- Translate system requirements into architecture, specifications, interfaces, and performance targets.
- Define microarchitecture, data paths, control paths, interfaces, clocking, reset, power, and error-handling mechanisms.
- Evaluate architectural trade-offs across performance, power, area, latency, bandwidth, scalability, and complexity.
- Define interfaces and protocols such as PCIe, UALink, AXI, APB, CHI, or other high-speed/interconnect protocols.
- Develop architecture specifications, block diagrams, interface specifications, and technical documentation.
- Work closely with RTL, verification, physical design, DFT, firmware, and system architecture teams.
- Identify architectural risks and drive resolution of complex technical issues.
- Review RTL and verification strategies to ensure implementation aligns with architectural intent.
- Provide technical leadership and mentorship to senior/principal engineers.
- Drive architecture reviews and communicate technical decisions to engineering leadership.
Required Skills
- Strong background in IP architecture and microarchitecture
- Background in ASIC/SoC architecture and microarchitecture is a big plus.
- Strong understanding of digital design, computer architecture, memory systems, interconnects, and SoC design.
- Experience with high-speed interfaces and/or coherent interconnects.
- Strong understanding of performance modeling, bandwidth, latency, and system-level trade-offs.
- Excellent technical communication and problem-solving skills.
Preferred
- Experience with PCIe, UALink, CXL, Ethernet, CCIX, CHI, or similar technologies.
- Experience with AI/accelerator, networking, compute, or high-performance SoC architectures.
- Experience taking IP/subsystems from architecture through silicon production.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
New roles in Bengaluru, last 12 weeks
- 20/7/2026 64
- 27/7/2026 76
- 3/8/2026 90
- 10/8/2026 93
- 17/8/2026 96
- 24/8/2026 111
- 31/8/2026 153
- 7/9/2026 134
- 14/9/2026 171
- 21/9/2026 165
- 28/9/2026 158
- 5/10/2026 236
- 12/10/2026 33
1580 vacancies. Source: Direct employer job feeds (ATS) and career sites crawled by gavroche-direct; vacancies by their own publication week.
Other roles at Astera Labs
- Product Technical Chip Lead - Senior Director · San Jose
- Senior ATE Test Engineer · San Jose
- Senior Principal Test Engineer · San Jose
- Senior Principal Photonics Test Engineer · San Jose
- Principal ATE Test Engineer · San Jose
- Distinguished Formal Verification · San Jose
123 open. Source: Direct employer job feeds (ATS) and career sites crawled by gavroche-direct.