← Back to all roles in India

Posted by the employer · Pune, India

Senior Software Engineer - Dataplane High Availability & Clustering

SonicWall · Pune · India

Software Engineer

Posted: 10/7/2026 · On the employer's job feed since 11/10/2026

The advert

Quoted in full from SonicWall's job posting. Gavroche does not edit it.

For more than 30 years, SonicWall has delivered a partner-first unified cybersecurity portfolio that helps SMBs, MSPs, and IT teams consolidate network security, endpoint security, security service edge (SSE), and threat response across hybrid environments. By bringing connected technology, real-time threat intelligence, automation, and expert services together, SonicWall helps organizations simplify security operations, achieve better security outcomes, and lower total cost of ownership. Backed by a global ecosystem of more than 17,000 partners, SonicWall delivers enterprise-grade protection built for SMB and mid-market realities. 

For more information, visit www.sonicwall.com or follow us on X, LinkedIn, Facebook, and Instagram. 

About the Role

SonicWall is seeking a Software Dev Senior Engineer (Dataplane) with deep expertise in High Availability, Fast-Path Packet Processing, and Distributed Systems to architect and optimize the dataplane HA subsystem across SonicWall NGFW hardware and virtual firewalls — driving sub-millisecond session state synchronization, zero-packet-loss failover, and line-rate forwarding for IPsec, SSL-VPN, and TCP/UDP flows at 10G–100G+.

Responsibilities

  • Dataplane HA Architecture — Own fast-path HA engine design covering Active/Standby mirroring, Active/Active flow redistribution, and zero-drop VMAC/VIP failover.
  • Stateful Session Mirroring — Build low-overhead dataplane sync for TCP/UDP 5-tuple tables, IPsec SA fast-path, SSL-VPN contexts, and L7 states across HA peers at line rate.
  • Lock-Free Session Tables — Design NUMA-aware, lock-free (RCU/CAS/seqlock) session tables for multi-core pipelines sustaining tens of millions of concurrent sessions at sub-microsecond latency.
  • High-Performance Sync Fabric — Engineer zero-copy ring buffer / DPDK mempool-based sync with prioritized queuing for IPsec/SSL-VPN state at sub-millisecond replication latency.
  • Asymmetric Flow Handling — Implement cross-node packet redirect, flow pinning, and state sync for asymmetric TCP/UDP and IPsec traffic in Active/Active topologies.
  • Hardware Offload Integration — Mirror offloaded SA/session state across HA peers for inline crypto engines (QAT, OCTEON, Nitrox) to preserve hardware acceleration post-failover.
  • Hitless Failover & ISSU — Ensure zero packet drops, zero IPsec renegotiations, and zero TCP resets during failover and In-Service Software Upgrades.
  • Technical Leadership — Drive dataplane HA architecture reviews, define benchmarks, author Specs, and mentor senior dataplane engineers.

Requirements

  • 7+ years of C/C++ development for high-performance networking dataplanes — firewalls, routers, switches, or carrier-grade appliances.
  • Dataplane HA & Fast-Path — Production experience with lock-free session mirroring, Active/Active packet steering, and stateful failover at 10G–100G+ line rates.
  • Packet Processing Frameworks — Deep hands-on with DPDK, ODP, OFP, or XDP/eBPF including zero-copy buffers, ring queues, and CPU core pinning.
  • Protocol Fast-Path — Expertise in IPsec SA fast-path lookups, SSL-VPN encapsulation/decapsulation, and TCP/UDP conntrack state synchronization.
  • Hardware Acceleration — Working knowledge of crypto offload engines (QAT, Marvell OCTEON, Cavium/Nitrox) or SmartNIC/DPU integration into packet pipelines.
  • Multi-Core & NUMA — Expert in cache-line alignment, lock-free concurrency, memory barriers, and NUMA-aware data structures for packet processors.
  • Debugging — Proficient with perf, GDB, ftrace, eBPF, tcpdump, and Wireshark for diagnosing dataplane race conditions and session continuity failures.

Nice to Have

  • Experience with NGFW dataplane HA (Palo Alto PAN-OS, Fortinet FortiOS, Cisco ASA/FTD, Check Point ClusterXL).
  • Cloud/virtual firewall dataplane HA (AWS SR-IOV, Azure Accelerated Networking, VMware ESXi DVS).
  • Exposure to 400GbE, SmartNIC, or DPU architectures (NVIDIA BlueField, Intel IPU).
  • Automated failure-injection and packet-level testing (IXIA, Spirent, TRex).

About the Role

SonicWall is seeking a Principal Engineer (Dataplane) with deep expertise in High Availability, Fast-Path Packet Processing, and Distributed Systems to architect and optimize the dataplane HA subsystem across SonicWall NGFW hardware and virtual firewalls — driving sub-millisecond session state synchronization, zero-packet-loss failover, and line-rate forwarding for IPsec, SSL-VPN, and TCP/UDP flows at 10G–100G+.

Responsibilities

  • Dataplane HA Architecture — Own fast-path HA engine design covering Active/Standby mirroring, Active/Active flow redistribution, and zero-drop VMAC/VIP failover.
  • Stateful Session Mirroring — Build low-overhead dataplane sync for TCP/UDP 5-tuple tables, IPsec SA fast-path, SSL-VPN contexts, and L7 states across HA peers at line rate.
  • Lock-Free Session Tables — Design NUMA-aware, lock-free (RCU/CAS/seqlock) session tables for multi-core pipelines sustaining tens of millions of concurrent sessions at sub-microsecond latency.
  • High-Performance Sync Fabric — Engineer zero-copy ring buffer / DPDK mempool-based sync with prioritized queuing for IPsec/SSL-VPN state at sub-millisecond replication latency.
  • Asymmetric Flow Handling — Implement cross-node packet redirect, flow pinning, and state sync for asymmetric TCP/UDP and IPsec traffic in Active/Active topologies.
  • Hardware Offload Integration — Mirror offloaded SA/session state across HA peers for inline crypto engines (QAT, OCTEON, Nitrox) to preserve hardware acceleration post-failover.
  • Hitless Failover & ISSU — Ensure zero packet drops, zero IPsec renegotiations, and zero TCP resets during failover and In-Service Software Upgrades.
  • Technical Leadership — Drive dataplane HA architecture reviews, define benchmarks, author Specs, and mentor senior dataplane engineers.

Requirements

  • 7+ years of C/C++ development for high-performance networking dataplanes — firewalls, routers, switches, or carrier-grade appliances.
  • Dataplane HA & Fast-Path — Production experience with lock-free session mirroring, Active/Active packet steering, and stateful failover at 10G–100G+ line rates.
  • Packet Processing Frameworks — Deep hands-on with DPDK, ODP, OFP, or XDP/eBPF including zero-copy buffers, ring queues, and CPU core pinning.
  • Protocol Fast-Path — Expertise in IPsec SA fast-path lookups, SSL-VPN encapsulation/decapsulation, and TCP/UDP conntrack state synchronization.
  • Hardware Acceleration — Working knowledge of crypto offload engines (QAT, Marvell OCTEON, Cavium/Nitrox) or SmartNIC/DPU integration into packet pipelines.
  • Multi-Core & NUMA — Expert in cache-line alignment, lock-free concurrency, memory barriers, and NUMA-aware data structures for packet processors.
  • Debugging — Proficient with perf, GDB, ftrace, eBPF, tcpdump, and Wireshark for diagnosing dataplane race conditions and session continuity failures.

Nice to Have

  • Experience with NGFW dataplane HA (Palo Alto PAN-OS, Fortinet FortiOS, Cisco ASA/FTD, Check Point ClusterXL).
  • Cloud/virtual firewall dataplane HA (AWS SR-IOV, Azure Accelerated Networking, VMware ESXi DVS).
  • Exposure to 400GbE, SmartNIC, or DPU architectures (NVIDIA BlueField, Intel IPU).
  • Automated failure-injection and packet-level testing (IXIA, Spirent, TRex).

 

#LI-DS9

#LI-Pune

#LI-HighAvailability

#LI-DPDK

 

 

SonicWall is an equal opportunity employer.  

We are committed to creating a diverse environment and are an equal opportunity employer. All qualified applicants receive consideration for employment without regard to race, color, ethnicity, religion, sex, gender, gender identity and expression, sexual orientation, national origin, disability, age, marital status, veteran status, pregnancy, or any other basis prohibited by applicable law.

At SonicWall, we pride ourselves on recruiting a diverse mix of talented people and providing active security solutions in 100+ countries.

Applicant Privacy Notice

Similar roles in Pune

200 open software engineer roles found; at most three per employer shown. Source: Direct employer job feeds (ATS) and career sites crawled by gavroche-direct.

How software engineer roles in India are worked

3% fully remote · 3% hybrid · 94% on-site

From 140 adverts whose ATS states a work mode. Source: Direct employer job feeds (ATS) and career sites crawled by gavroche-direct; the employers' own work-mode flags (adverts without one count as on-site).

New roles in Pune, last 12 weeks

  1. 20/7/2026 8
  2. 27/7/2026 9
  3. 3/8/2026 6
  4. 10/8/2026 16
  5. 17/8/2026 19
  6. 24/8/2026 20
  7. 31/8/2026 23
  8. 7/9/2026 23
  9. 14/9/2026 33
  10. 21/9/2026 44
  11. 28/9/2026 49
  12. 5/10/2026 31
  13. 12/10/2026 37

318 vacancies. Source: Direct employer job feeds (ATS) and career sites crawled by gavroche-direct; vacancies by their own publication week.

Other roles at SonicWall

29 open. Source: Direct employer job feeds (ATS) and career sites crawled by gavroche-direct.