Bengaluru, India
Principal Physical Design Engineer - RTL-to-GDSII
EnCharge AI · Bengaluru · India
Posted: 19/2/2026 · Last checked: 12/10/2026
Job description
Quoted in full from EnCharge AI's job posting. Gavroche does not edit it.
EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.
Key Responsibilities
- Full-Flow Ownership: Lead the implementation of massive, high-speed blocks/SoCs from Synthesis through Sign-off using the Cadence Digital Suite.
- PPA Optimization: Push the theoretical limits of the PDK and tools. You will analyze and optimize the interplay between library cells, metal stacks, and tool engines to squeeze out every millivolt and picosecond.
- Methodology & Scalability: Build and refine a "Push-Button" style execution methodology that is robust, repeatable, and minimizes manual "human-in-the-loop" iterations.
- Cross-Functional "Left-Shift": Collaborate with RTL, Architecture, and DFT teams to influence design decisions early. You will drive a holistic approach where physical constraints inform the architecture, not just react to it.
- Bottleneck Elimination: Identify "drag" in the execution pipeline—whether it’s runtime, convergence issues, or tool limitations—and architect automated solutions to bypass them.
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Experience
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14+ years in Physical Design with a proven track record of multiple sub-5nm tape-outs.
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Tool Suite
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Mastery of Cadence Innovus, Tempus, Joules, Pegasus, and Voltus.
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Advanced Nodes
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Deep understanding of sub-5nm physics: EUV constraints, multi-patterning, FinFET and IR/EM challenges.
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Sign-off
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Expert-level knowledge in Static Timing Analysis (STA), Physical Verification (PV), and Power Integrity (PI) and ECO methodology.
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Scripting
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Proficiency in Tcl and Python to develop custom flow wrappers and data-mining tools for PPA analysis.
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- Holistic Thinking: You look at the "Big Picture." You solve timing by fixing the floorplan or the RTL/ARCH
- Influence & Rapport: You can build strong technical bridges with Front-End, Foundry, and EDA vendors to align on a unified execution strategy.
- Critical Thinking: You operate on first principles. You don't just follow a vendor's "Best Practices" if they don't make sense for our specific architecture.
- Mentorship: You act as a force multiplier, elevating the technical competence of the entire PD team.
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